Domain-specific compute
Explore small RISC-V extensions, low-power accelerators, and fixed-latency datapaths for real-time systems.
RESEARCH PROGRAM / 01
Design compute.
Prove every bit.
An open research initiative exploring how autonomous engineering agents can design, verify, and improve specialized processors—from RTL to physical silicon.
FOUNDING PHASE · OPEN RESEARCH ROADMAP
FIG. 01 / SILICON RESEARCHCONCEPT ILLUSTRATION / NOT A MEASURED RESULT
RESEARCH DOMAIN
Autonomous Processor Research
CURRENT STAGE
01 / FOUNDATION
METHOD
Hypothesis → experiment → evidence
THE MISSION
Real engineering. Measurable evidence.
Make useful processor architecture discoverable, testable, and eventually manufacturable through autonomous engineering.
Can an AI research system propose a hardware architecture, verify its correctness, and demonstrate measurable gains over an honest baseline?
We treat AI-generated engineering ideas as hypotheses, not accomplishments. The research loop demands explicit assumptions, independent tests, reproducible artifacts, and comparison with strong conventional methods. No performance claim is published without a traceable experiment.
THE RESEARCH AGENDAThree frontiers.
Three frontiers.
One rigorous method.
A focused technical agenda, structured to produce useful open research artifacts rather than speculative demonstrations.
Agent-directed EDA
Connect structured agent proposals to RTL generation, testbenches, synthesis, and design-space exploration.
Measured performance
Compare area, timing, estimated power, and functional correctness with versioned artifacts.
How each research cycle works
DESIGN
Generate constrained microarchitecture candidates and inspect the tradeoffs.
VERIFY
Prove functional behavior against independent reference models and randomized tests.
MEASURE
Run synthesis and physical-design estimates with reproducible toolchains.
EVOLVE
Retain evidence-backed improvements; reject candidates that fail verification.
THE ROADMAP
From first principles to demonstrated capability.
Milestones are intentions, not achieved results. Progress and benchmark evidence will be added as they become independently verifiable.
I / FOUNDATIONCURRENT FOCUS
FOUNDATION
Reproducible RTL baseline, CI, and formalized design constraints
II / SEARCHPLANNED
SEARCH
Automated architecture candidate generation and selection
III / PROTOTYPEFUTURE
PROTOTYPE
FPGA validation of selected designs
IV / SILICONLONG-TERM
SILICON
Assess tape-out options after measured feasibility